In the semiconductor fabrication technology, various devices built on a chip must be connected in a specific configuration in order to form a desired circuit. The formed circuit must also be accessible to an outside circuit through conducting pads for testing by metal probes and for bonding to conductive bumps in order to complete a packaged chip. Even though widely used doped silicon and polysilicon conduct electricity, they are of very limited use as interconnections because of their prohibitively high electrical resistance and their lack of interconnecting flexibility.
In a semiconductor device, usually at least one low resistance conducting film must be deposited and patterned to form contacts and interconnects throughout different regions in the chip. Many single metal systems such as aluminum, tungsten, copper, etc. and their alloys are available for this purpose. Among these metals, aluminum is a popularly used interconnect material due to its high conductivity, its compatibility with silicon-based technology, and its low processing costs.
In a simplified form, a metalization process can be carried out by first covering a wafer with an insulating layer, contacting and etching openings in the insulating layer, and then depositing and defining an aluminum film to form both contacts and interconnects. In modern semiconductor devices where dimensions are continuously shrinking and devices are more densely packed together, the layout and the utilization of a metalization system can become dominant factors in determining the circuit density and speed. Major factors that determine a metalization system are the contacting scheme, the inter-level dielectrics, the interconnecting metals, and the reliability of the metalization system.
The metal materials used in building interconnects must satisfy certain basic requirements in order to meet the criteria of circuit performance, fabrication yield and product reliability. The metal should have low series and contact resistance, electromigration into the silicon, satisfactory adhesion to insulators and contacted surfaces, good uniformity and resistance to corrosion. Two of the more commonly used metal materials for interconnects and contacts are aluminum alloys and tungsten. Aluminum can meet most of the performance requirements of an interconnect but suffers a deficiency known as electromigration which can be minimized by adding a small amount of copper into aluminum to form an alloy. Tungsten, even though is less susceptible to electromigration and has great conformity during deposition has a significantly higher electrical resistivity than aluminum. It is therefore only used in lower-level metals. Copper has also been used in interconnects because of its superior conductivity and higher electromigration resistance than aluminum. However, copper is difficult to delineate and therefore is normally cladded with a barrier metal to inhibit its diffusion into oxide and silicon.
The metal interconnects can be formed by various deposit on methods such as an evaporation technique, a sputtering technique or a chemical vapor deposition technique. An improved technique of collimated sputtering can also be used. The sputtering technique is widely used in depositing aluminum and its alloys due to its high deposition rate, uniform step coverage and contact hole filling capabilities. The collimated sputtering technique ensures that sufficient metal particles cover the bottom of a high aspect-ratio contact before the material blocks the top of the opening.
After a metal material such as an aluminum alloy of Al--Cu--Si or Al--Cu is deposited onto a film in a semiconductor device, a layer of photoresist masking is deposited on the surface of the metal layer to perform subsequent lithographic and reactive ion etching (RIE) processes to create openings. This is widely used in the DRAM metalization patterning process for building interconnects. The degree of success of such a process depends on the capability of generating a reproducible and consistent sidewall on the metal during the RIE process when the sidewall acts as a barrier to isotropic undercut by the RIE chemicals.
Referring initially to FIG. 1, wherein a conventional metalization process on a silicon wafer is shown. A semiconductor device 10 having a silicon substrate 12, a metal layer 14, and a photoresist layer 16 deposited on top is shown. After an opening 22 is etched into the metal layer 14 by using the pattern in the photoresist layer 16, chemical compound 24 of a corrosive nature is frequently formed to cover the metal surface 26 in the opening 22. The chemical compound 24 is formed by a reaction between the photoresist film which is frequently a hydrocarbon polymer and the chlorine or fluorine molecules contained in the reactive ion etching chemicals. The reactive ion etching technique is a frequently used etching technique in the manufacture of densely packed semiconductor devices. In reactive ion etching, positive plasma ions generated in a parallel-plate RF reactor are used to provide a source of energetic particles bombardment on the surface to be etched and producing a fairly vertical etch in the film with minimal undercutting. The ion bombardment process increases the reaction rate of spontaneously occurring processes and prompts reactions which would otherwise proceed at a much slower rate without radiation. In a reactive ion etching reactor, the wafer is placed on a powered electrode of a parallel-plate RF reactor. The horizontal surface of the wafer is subjected to both the reactant chemical species and their impinging ions, while the vertical sidewalls are only subjected to reactive species. This is one reason that fairly vertical openings can be obtained in an etched film.
The chemical compound 24 of a corrosive nature coated on the inside wall 26 of the metal layer 14 at opening 22 can cause metal corrosion problems. This presents a serious drawback to the process especially when aluminum is used as the metal interconnect material due to its poor corrosion resistance. For instance, in a conventional aluminum metalization process, aluminum metal particles are first sputtered deposited on a substrate 12. A photoresist layer 16 is then deposited on top of the metal layer 14 and patterned by a photolithography process. After windows are opened in the metal layer 14 by a reactive ion etching process, the photoresist layer 16 is stripped off the metal layer 14 by a solvent based cleaning method. The aluminum metal layer 14 is then oxidized to form aluminum oxide in order to stop any further corrosion of the metal. This practice is sometimes called a surface passivation process. After the device is rinsed by deionized water, the metal layer 14 is annealed to improve the metal quality by relieving stress and improving the electrical conductance. The device is then blanket deposited in a chemical vapor deposition process a layer of an inter-layer dielectric material to complete the fabrication. As stated previously, when chemical compound 24 of a corrosive nature covers the metal surface 26 at the opening 22, it would prevent or slow down the aluminum oxidization process due to the corrosion on the aluminum surface 24. Since the success of a RIE process depends very much on its capability to generate a reproducible and consistent sidewall during the etch (which acts as a barrier to isotropic undercut), the chemical compound formed by the interaction of a photoresist mask with the RIE chemistry which corrodes the sidewall and effectively widens the resist image. The end result is a final etched feature that is wider than the resist image by a component of the etch bias. Furthermore, the corrosive compound on the sidewall may become infused with the active etchant during RIE that it must be throughly passivated by a post-RIE processing step prior to venting of the chamber, in order to prevent the initiation of aluminum corrosion reactions.
It is therefore an object of the present invention to provide a method for forming metalization for inter-layer connections in a semiconductor device that does not have the drawbacks and shortcomings of conventional metalization processes.
It is another object of the present invention to provide a method for forming metalization for inter-layer connections in a semiconductor device by first depositing a dielectric layer on top of a metal layer for use as the masking film in the reactive ion etching of the metal layer.
It is a further object of the present invention to provide a method for forming metalization for inter-layer connections in a semiconductor device that does not have a metal corrosion problem caused by chemical compound formed between a photoresist material and the RIE chemicals.
It is yet another object of the present invention to provide a method for forming metalization for inter-layer connections in a semiconductor device by depositing an additional dielectric material layer immediately adjacent to the metal layer.
It is still another object of the present invention to provide a semiconductor structure that includes a substrate, a metal layer, a dielectric layer deposited on the metal layer and an opening through the metal layer and the dielectric layer exposing the substrate.